Motivation

Problems with existing MT/parallel approaches

Having worked on a few SMP parallel processing projects using pThreads and Quickthreads with C/C++, it became obvious fairly quickly that there are a number of problems with the approach:

Very hard to debug with more than a few threads running
Very expensive in CPU with a lot of threads due to the context switch overhead
Very hard to statically analyze or formally verify because of the dynamic nature of C/C++ code

The reason that people use pThreads is (of course) historic, the general method of extension in C is to add functionality through external libraries, so pThreads is just a layer over the operating system's own internal multi-threading/process management that is also used for more general (heavy-weight) process management. The fundamental flaw in the approach is that the pThreads libraries take a routine as the thread entry point, create a new stack frame and then call the routine on the new stack, this causes threads to have a large memory footprint and often odd bugs due to the stack being of limited depth.

Multi-Threaded Languages

There are a couple of well known multi-threaded programming languages: Verilog and VHDL. These are better known as hardware description languages (HDLs). Hardware descriptions are different from normal coding in that the description is intrinsically parallel (with a large number of threads) and entirely static.

Both Verilog and VHDL have their roots back in the 1980s and have semantic description problems that are tied to assumptions made at that time:

No power management (as required in most modern designs)
Limited back-annotation (feedback of manufacturing effects)
Analog was an afterthought (so not well integrated)
Limited availability and lack of native compile (no equivalent of GCC for full language)
Limited support for RF/Wireless modeling

ESL Language - The "Holy Grail" ?

Electronic Systems Level (ESL) methodology wants to look at the design process for systems from software down to Silicon in a wholistic way. To do this cleanly requires a single language that is usable as a programming language and also as an HDL.

Most ESL designers work with SystemC (a C++ HDL class library) which suffers from the problems mentioned in the first paragraph above.

An attempt was made to merge C and Verilog in the language SuperLog which later morphed into rev 1 of SystemVerilog. Unfortunately rev 2 went in other directions, so SystemVerilog is not really usable as an ESL language.

ParC

ParC came out of the observation that the evolution of HDLs was simply the addition of features from programming languages (like C and Java). In order to create a usable ESL language (as in: liked by programmers), it would be necessary to added the features of an HDL to an existing programming language. C++ is the prime candidate for this because of symmetries between the "class" syntax/semantics and modules/tasks in Verilog/VHDL.

ParC is therefore intended to be a functional superset of Verilog and VHDL (for at least the parts used for actual hardware description). The new constructs being added to C++ are clean implementations of the abstractions needed for hardware description and synthesis.