Methodology

Verification

In a typical HDL based flow, a high level description is converted by synthesis tools into a low level (logic cell) representation. For ESL this will often also involve a transition from SystemC to Verilog, in which case it is highly likely that any verification environment that exists for the SystemC won't work with the Verilog. Because ParC can be used for the high level representation as well as the low level representation, any verification tools that work with the high level code will work with the low level version too.

Compilation & Synthesis

In general synthesis or code morphing with ParC should be done so that the result of translation is also ParC, but that ParC has a simple 1-to-1 mapping to the target hardware. This allows verification of the ParC description on a platform that supports debugging prior to deployment on a platform that doesn't, i.e. FPGAs and GP-GPUs usually have poor debugging support, so being able to debug the same code description on an SMP desktop machine is important. ParC can be used to model the target hardware, so the final code mappings can also be tested in the same environment (using ParC virtual machines).

Runtime Management

Since FPGA and GP-GPU support is unlikely to be consistent (different capacity/vendor on different platforms), it's useful to be able to load up the code on a general purpose machine first and then move parts of it on and off whatever accelerating hardware is available. In the case of a program being swapped in and out one would expect the program to be loaded as any other would by the OS and then the runtime management would migrate all or part of it onto available accelerators, when the program needs to be swapped out it would first transfer back off the accelerators so that it is running like a normal program. In a demand based (event driven) computing environment this means that a program can easily surrender hardware it doesn't need while still running, and in a power sensitive environment an application can shrink it's usage of hardware to the minimum necessary to maintain required performance.